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Figure 25.1. ADC Overview
ADCn_CTRL
ADCn_CMD
ADCn_SINGLECTRL
ADCn_SINGLEDATA
ADCn_SCANDATA
ADCn_STATUS
ADCn_SCANCTRL
Oversam pling
filter
HFPERCLK ADCn
Prescaler
ADC_CLK
Sequencer
Result
buffer
ADCn_CH0
ADCn_CH1
ADCn_CH2
ADCn_CH3
ADCn_CH4
ADCn_CH5
ADCn_CH6
ADCn_CH7
Tem p
+
-
Contro l
SAR
V DD /3
V DD
V SS
V ref /2
DAC0
DAC1
V DD
1.25 V
2.5 V
5 V differential
2x(VDD-VSS)
25.3.1 Clock Selection
The ADC has an internal prescaler (PRESC bits in ADCn_CTRL) which can divide the peripheral clock
(HFPERCLK) by any factor between 1 and 128. Note that the resulting ADC_CLK should not be set to
a higher frequency than 13 MHz and not lower than 32 kHz.
25.3.2 Conversions
A conversion consists of two phases. The input is sampled in the acquisition phase before it is converted
to digital representation during the approximation phase. The acquisition time can be configured
independently for scan and single conversions (see Section 25.3.7 (p. 347) ) by setting AT in
ADCn_SINGLECTRL/ADCn_SCANCTRL. The acquisition times can be set to any integer power of 2
from 1 to 256 ADC_CLK cycles.
Note
For high impedance sources the acquisition time should be adjusted to allow enough time
for the internal sample capacitor to fully charge. The minimum acquisition time for the
internal temperature sensor and V dd /3 is given in the electrical characteristics for the device.
The analog to digital converter core uses one clock cycle per output bit in the approximation phase.
ADC Total Conversion Time (in ADC_CLK cycles) Per Output
T conv = (T A +N) x OSR
(25.1)
T A equals the number of acquisition cycles and N is the resolution. OSR is the oversampling ratio (see
Section 25.3.7.7 (p. 349) ). The minimum conversion time is 7 ADC_CYCLES with 6 bit resolution and
13 ADC_CYCLES with 12 bit resolution. The maximum conversion time is 1097728 ADC_CYCLES with
the longest acquisition time, 12 bit resolution and highest oversampling rate.
2011-04-12 - d0001_Rev1.10
343
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